In many electrical control systems it is important to synchronize or couple two different signals to each other, for instance this is of interest in radio, telecommunications, and computers where it is of interest to stable frequencies, recover signals, and provide clock timing signals respectively. In these applications it is of interest to provide an output signal whose phase and/or frequency match a reference signal.
In telecommunications technology where different coding schemes are used it is important to synchronize communication data with a decoder in order to extract useful data. One of the components that are part of this synchronization process is a phase-locked loop (PLL) device.
For example, in telecommunication, the Phase-Locked Loop (PLL) is used to generate clocks that have fixed phase/frequency relationship with an input reference clock signal as compared to a feedback clock signal of the PLL. A typical PLL system is a negative control system comparing the feedback clock signal with the reference clock signal; for instance a PLL may comprise a Phase Frequency Detector (PFD), a voltage control oscillator (VCO) providing the feedback clock signal connected in a feedback path to the PFD. The PFD receives the reference and feedback clock signals and detects the frequency and phase error between the input reference clock and the feedback clock. The PLL generates an error signal which will be used to adjust the VCO so that the phase/frequency of the output/feedback clock will be the same or within a suitable range as the reference clock, which is said to then lock to the reference clock, i.e. the error between the feedback and reference clocks are substantially zero. The PLL may be locked in a first iteration or it may require a number of iterations before the feedback clock signal is suitably close to the reference signal in order to be determined as locked. The phase is the derivative of the frequency meaning there is a direct relationship between the two.
A phase-locked loop solution based on a charge-pump is for instance described in “Charge-Pump Phase-Lock Loops” in IEEE Transactions on Communications, vol. corn-28, no. 11, November 1980 and a general description of phase-locked loops may be found in “Phase-Locked Loops: A Control Centric Tutorial” from the Proceedings of the 2002 ACC. These may provide a basic understanding of PLL circuits and their applications.
Given a constant loop gain, the PLL lock time is related to the frequency of the reference clock. For typical PLLs, the lower the frequency of the reference clock is, the slower the convergence speed will be. Hence a typical PLL is not efficient for ultra-low frequency clocks, for example, 1 pulse per second signal (1 PPS signal), i.e. it will take long time before the output/feedback clock lock to the reference clock.